As dynamic random access memory (DRAM) devices become more highly integrated, the sizes of individual memory cells are reduced. The decrease in size of a memory cell is thus proportional to the increase in the capacity of a DRAM device. As the surface area of the integrated circuit substrate available for each memory cell is reduced, the height of the stacked chip structure may increase.
In order to provide normal memory device operation, the capacitance of the memory cell capacitors and the voltage applied to the elements of the memory device are preferably maintained at predetermined levels as the integration densities increase. Stated in other words, effective voltage ranges and capacitances for the elements of highly integrated DRAM devices should be maintained at predetermined levels as the size of the device elements are reduced. Accordingly, more complex device structures may be needed to provide a desired level of performance in a highly integrated DRAM device. Unit cell structures including a memory cell capacitor and a memory cell access transistor have changed significantly as higher levels of integration have been obtained.
For example, a memory cell capacitor for a 1M DRAM device may have a dielectric layer having a planar silicon oxide layer structure. A memory cell capacitor for a 4M DRAM may have a dielectric layer having a stacked O-N-O layered structure wherein silicon oxide and silicon nitride layers are stacked. A memory cell capacitor for a 16M DRAM device may have a dielectric layer having a stacked N-O layered structure wherein a silicon nitride layer and a silicon oxide layer are stacked. The memory cell capacitor for a 64M DRAM may have a dielectric layer having a cylindrical N-O layered structure or a stacked N-O layered structure on an electrode having hemispherical grains (HSG). Memory cell capacitors for 245M and 1 G DRAM devices may include three-dimensional electrode structures such as stacked, cylindrical, or capacitor-on-bit-line structures together with hemispherical grain (HSG) electrode surfaces and ferroelectric dielectric layers.
As will be understood by one having skill in the art, a capacitor includes two electrodes and a dielectric layer therebetween. The capacitance is directly proportional to the permittivity of the dielectric layer and the surface area of the electrodes. The capacitance is inversely proportional to the thickness of the dielectric layer.
Conventional dielectric layers have been provided using silicon oxide layers, silicon nitride layers, and combinations thereof. More recently, ferroelectric materials such as Ta.sub.2 O.sub.5 have been used to provide dielectric layers. These ferroelectric materials may have a permittivity three to four times higher than that of silicon nitride allowing an increase in capacitance.
Ferroelectric materials, however, have been difficult to use in certain DRAM applications, and it may difficult to reduce the thickness of a dielectric layer beyond a certain point. Accordingly, past attempts to increase memory cell capacitance have been primarily directed to increasing the surface area of the capacitor electrodes. In particular, conventional planar electrode structures have been replaced by three-dimensional structures or by providing structural distortions thereon. For example, stacked electrode structures, trench electrode structures, cylindrical electrode structures, and capacitor-on-bit-line electrode structures have been used to increase capacitor electrode surface areas.
The development of these three-dimensional electrode structures, however, may require more complicated processing steps. accordingly, these three-dimensional structures may result in increased expense due to the increased complexity of the processing steps and design rule limitations. Furthermore, sufficiently large and predictable capacitances may be difficult to obtain using these three-dimensional structures in a highly integrated memory device.
Capacitor electrode surface areas have also been increased by providing hemispherical grains on the surfaces of the electrodes. The use of hemispherical grains (HSG) on a capacitor electrode has been discussed by Watanabe in the reference entitled "Hemispherical Grained Silicon Formation On In-Situ Porous Doped Amorphous-Si Using The Seeding Method". SSDM, 1992, pp. 422-424. As discussed, silicon forms hemispherical-shaped regions due to silicon migration in the transition temperature range of crystalline silicon and amorphous silicon, as the surface energy is most stable in this range. The formation of the hemispherical grains produces a rough surface having a plurality of protrusions which are formed from a surface active silicic gas such as Si.sub.2 H.sub.6, SiH.sub.4 or silicon inside the layers. The surface active silicic gas uses some structurally abnormal or deposited particles of the wafer surface as seeds to enlarge the capacitor surface thereby increasing the capacitance of the capacitor including the electrodes having rough surfaces. Difficulties, however, may result from the use of electrodes having hemispherical grains thereon.
For example, when the lower electrode of the capacitor is doped, the size of the hemispherical grains may increase resulting in the reduction of capacitance due to insufficient impurity diffusion outside the lower electrode. When the lower electrode is doped by a POCl.sub.3 deposition, however, a wet etch may be needed to remove a P.sub.2 O.sub.5 layer formed thereon. This wet etch may abrade some of the protrusions hereby reducing the effect of the capacitor electrode enlargement. The protrusions can also be abraded by the impact of implanted ions.
In addition, the hemispherical grains may be formed between the lower electrodes wherein the hemispherical grains are formed on the lower electrode surfaces thereby shorting lower electrodes. A dry etch may thus be needed to remove hemispherical grained silicon portions on the insulating layer between the lower electrodes. This dry etch, however, may also etch the hemispherical grains formed on the electrode surface thereby reducing the enlargement of the electrode surface area.
Furthermore, the hemispherical grains may also form on the backside of the semiconductor substrate when using a low pressure chemical vapor deposition (LPCVD) to form the hemispherical grains. Accordingly, there is an increased probability that the hemispherical grains may generate particles during subsequent processing steps. Additional processing steps such as backside coating, wet etching, and backside coating removal have been used to reduce the formation of hemispherical grains on the backside of the substrate. The formation of hemispherical grains may also involve steps having relatively narrow processing margins. In particular, hemispherical grains may be formed at the transition temperature of amorphous silicon to polysilicon. The formation of the hemispherical grains is thus sensitive to the temperature controls so that it may be difficult to maintain a uniform size and density of hemispherical grains from wafer to wafer and run to run. Accordingly, there continues to exist a need in the art for improved methods of increasing memory cell capacitances.